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| EL4581C EL4581C Sync Separator 50% Slice S-H Filter Features NTSC PAL and SECAM sync separation Single supply a 5V Precision 50% slicing internal caps Built-in color burst filter Decodes non-standard verticals Pin compatible with LM1881 Low power Typically 1 5 mA supply current Resistor programmable scan rate Few external components Available in 8-pin DIP and SO-8 pkg General Description The EL4581C extracts timing information from standard negative going video sync found in NTSC PAL and SECAM broadcast systems It can also be used in non standard formats and with computer graphics systems at higher scan rates by adjusting a single external resistor When the input does not have correct serration pulses in the vertical interval a default vertical output is produced Outputs are composite sync vertical sync burst back porch output and odd even output The later operates only in interlaced scan formats The EL4581C provides a reliable method of determining correct sync slide level by setting it to the mid-point between sync tip and blanking level at the back porch This 50% level is determined by two internal self timing sample and hold circuits that track sync tip and back porch levels This also provides a degree of hum and noise rejection to the input signal and compensates for varying input levels of 0 5 p-p to 2 0 Vp-p A built in linear phase third order low pass filter attenuates the chroma signal in color systems to prevent incorrectly set color burst from disturbing the 50% sync slide This device may be used to replace the industry standard LM1881 offering improved performance and reduced power consumption The EL4581C video sync separator is manufactured using Elantec's high performance analog CMOS process Applications Video special effects Video test equipment Video distribution Displays Imaging Video data capture Video triggers Ordering Information Part No Temp Range Package Outline EL4581CN b 40 C to a 85 C 8-Pin DIP MDP0031 EL4581CS b 40 C to a 85 C 8-Lead SO MDP0027 Connection Diagram EL4581C SO P-DIP Packages Demo Board A dedicated demo board is not available However this device can be placed on the EL4584 5 Demo Board January 1996 Rev B 4581 - 1 Top View Manufactured under U S Patent No 5 528 303 Note All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication however this data sheet cannot be a ``controlled document'' Current revisions if any to these specifications are maintained at the factory and are available upon your request We recommend checking the revision level before finalization of your design documentation 1993 Elantec Inc EL4581C Sync Separator 50% Slice S-H Filter Absolute Maximum Ratings (TA e 25 C) VCC Supply Storage Temperature Lead Temperature 7V b 65 C to a 150 C Pin Voltages b 0 5V to VCC a 0 5V Operating Temperature Range b 40 C to a 85 C 260 C Important Note All parameters having Min Max specifications are guaranteed The Test Level column indicates the specific device testing actually performed during production and Quality inspection Elantec performs most electrical tests using modern high-speed automatic test equipment specifically the LTX77 Series system Unless otherwise noted all tests are pulsed tests therefore TJ e TC e TA Test Level I II III IV V Test Procedure 100% production tested and QA sample tested per QA test plan QCX0002 100% production tested at TA e 25 C and QA sample tested at TA e 25 C TMAX and TMIN per QA test plan QCX0002 QA sample tested per QA test plan QCX0002 Parameter is guaranteed (but not tested) by Design and Characterization Data Parameter is typical value at TA e 25 C for information purposes only DC Electrical Characteristics Unless otherwise state VDD e 5V Parameter IDD Clamp Voltage Discharge Current Clamp Charge Current Ref Voltage VOL Output Low Voltage VOH Output High Voltage Description VDD e 5V (Note 1) Pin 2 Unloaded Pin 2 e 2V Pin 2 VIN e 1V Pin 6 VDD e 5V (Note 2) IOL e 1 6 mA IOH e b40 mA IOH e b1 6 mA Temp 25 C 25 C 25 C 25 C 25 C 25 C 25 C 4 24 Min 0 75 13 6 2 15 TA e 25 C Rset e 680 kX Typ 17 15 10 3 18 21 800 Max 3 19 20 Test Level I I I I I I IV I Units mA V mA mA V mV V TD is 1 8in Note 1 No video signal outputs unloaded Note 2 Tested for VDD 5V g5% which guarantees timing of output pulses over this range 2 EL4581C Sync Separator 50% Slice S-H Filter Dynamic Characteristics VDD e 5V IV pk-pk video TA e 25 C CL e 15 pF IOH e b1 6 mA IOL e 1 6 mA Signal voltages are peak to peak Parameter Vertical Sync Width tVS Burst Back Porch Width tB Vertical Sync Default Delay tVSD Filter Attenuation Composite Sync Prop Delay Input Dynamic Range Slice Level Note Note Note Note 3 4 5 6 FIN e 3 4 MHz (Note 4) VINb Composite Sync (Note 3) p-p NTSC Signal (Note 5) Input Voltage e 1VP-P (Note 6) Description (Note 3) (Note 3) Temp 25 C 25 C 25 C 25 C 25 C 25 C 25 C Full 05 40% 40% 50% 50% Min 190 25 40 Typ 230 35 55 24 260 400 2 60% 60% Max 300 45 70 Test Level I I I V I I I IV Units ms ms ms dB ns V C S Vertical and Burst outputs are all active low b VOH e 2 4V VOL e 0 8V Attenuation is a function of Rset (PIN6) Typical min is 0 3 VP-P Refers to threshold level of sync tip to back porch amplitude Pin Descriptions Pin No 1 2 3 4 5 6 7 8 Pin Name Composite Sync Out Composite Video in Vertical Sync Out GND Burst Back Porch Output RSET Odd Even Output VDD 5V Function Composite sync pulse output Sync pulses start on a falling edge and end on a rising edge AC coupled composite video input Sync tip must be at the lowest potential (Positive picture phase) Vertical sync pulse output The falling edge of Vert Sync is the start of the vertical period Supply ground Burst Back porch output Low during burst portion of composite video An external resistor to ground sets all internal timing 681k 1% resistor will provide correct timing for NTSC signals Odd Even field output Low during odd fields high during even fields Transitions occur at start of Vert Sync pulse Positive supply (5V) Note RSET must be a 1% resistor 3 TD is 2 0in EL4581C Sync Separator 50% Slice S-H Filter Typical Performance Characteristics RSET vs Horizontal Frequency Back Porch Clamp On Time vs RSET Vertical Pulse Width vs RSET Vertical Default Delay Time vs RSET Vertical Pulse Width vs Temperature Supply Current vs Temperature Input Signal e 300 mVP-P EL4581 Filter Characteristic Constant Delay 240 ns 4581 - 2 4 EL4581C Sync Separator 50% Slice S-H Filter Timing Diagrams 4581 - 3 Figure 1 Notes b The composite sync output reproduces all the video input sync pulses with a propagation delay c Vertical sync leading edge is coincident with the first vertical serration pulse leading edge with a propagation delay d Odd-even output is low for even field and high for odd field e Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses Note that for serration pulses during vertical the back porch starts on the rising edge of the serration pulse (with propagation delay) 5 EL4581C Sync Separator 50% Slice S-H Filter 4581 - 5 Figure 2 4581 - 6 Figure 3 6 EL4581C Sync Separator 50% Slice S-H Filter 4581 - 7 Figure 4 Standard (NTSC Input) H Sync Detail 7 EL4581C Sync Separator 50% Slice S-H Filter Description of Operation A simplified block schematic is shown in Figure 2 The following description is intended to provide the user with sufficient information to be able to understand the effects that the external components and signal conditions have on the outputs of the integrated circuit The video signal is AC coupled to pin 2 via the capacitor C1 nominally 0 1 mF The clamp circuit A1 will prevent the input signal on pin 2 going any more negative than 1 5V the value of reference voltage VR1 Thus the sync tip the most negative part of the video waveform will be clamped at 1 5V The current source I1 nominally 10 mA charges the coupling capacitor during the remaining portion of the H line approximately 58 ms for a 15 75 kHz timebase From I t e C V the video time-constant can be calculated It is important to note that the charge taken from the capacitor during video must be replaced during the sync tip time which is much shorter (ratio of x 12 5) The corresponding current to restore the charge during sync will therefore be an order of magnitude higher and any resistance in series with CI will cause sync tip crushing For this reason the internal series resistance has been minimized and external high resistance values in series with the input coupling capacitor should be avoided The user can exercise some control over the value of the input time constant by introducing an external pull-up resistance from pin 2 to the 5V supply The maximum voltage across the resistance will be VDD less 1 5V for black level For a net discharge current greater than zero the resistance should be greater than 450k This will have the effect of increasing the time constant and reducing the degree of picture tilt The current source I1 directly tracks reference current ITR and thus increases with scan rate adjustment as explained later The signal is processed through an active 3 pole filter (F1) designed for minimum ripple with constant phase delay The filter attenuates the color burst by 24 dB and eliminates fast transient spikes without sync crushing An external filter is not necessary The filter also amplifies the video signal by 6 dB to improve the detection accuracy Note that the filter cut-off frequency is a function of RSET through IOT and is proportional to IOT Internal reference voltages (block VREF) with high immunity to supply voltage variation are derived on the chip Reference VR4 with op-amp A2 forces pin 6 to a reference voltage of 1 7V nominal Consequently it can be seen that the external resistance RSET will determine the value of the reference current ITR The internal resistance R3 is only about 6 kX much less than RSET All the internal timing functions on the chip are referenced to ITR and have excellent supply voltage rejection Comparator C2 on the input to the sample and hold block (S H) compares the leading and trailing edges of the sync pulse with a threshold voltage VR2 which is referenced at a fixed level above the clamp voltage VR1 The output of C2 initiates the timing one-shots for gating the sample and hold circuits The sample of the sync tip is delayed by 0 8 ms to enable the actual sample of 2 ms to be taken on the optimum section of the sync pulse tip The acquisition time of the circuit is about three horizontal lines The double poly CMOS technology enables long time constants to be achieved with small high quality on-chip capacitors The back porch voltage is similarly derived from the trailing edge of sync which also serves to cut off the tip sample if the gate time exceeds the tip period Note that the sample and hold gating times will track RSET through IOT The 50% level of the sync tip is derived through the resistor divider R1 and R2 from the sample and held voltages VTIP and VBP and applied to the plus input of comparator C1 This comparator has built in hysteresis to avoid false triggering The output of C2 is a digital 5V signal which feeds the C S ouput buffer B1 and the other internal circuit blocks the vertical back porch and odd even functions The vertical circuit senses the C S edges and initiates an integrator which is reset by the shorter horizontal sync pulses but times out the longer 8 EL4581C Sync Separator 50% Slice S-H Filter Description of Operation Contd vertical sync pulse widths The internal timing circuits are referenced to IOT and VR3 the timeout period being inversely proportional to the timing current The vertical output pulse is started on the first serration pulse in the vertical interval and is then self-timed out In the absense of a serration pulse an internal timer will default the start of vertical The back porch is triggered from the sync tip trailing edge and initiates a one-shot pulse The period of this pulse is again a function of IOT and will therefore track the scan rate set by RSET The odd even circuit (O E) comprises of flip flops which track the relationship of the horizontal pulses to the leading edge of the vertical output and will switch on every field at the start of vertical Pin 7 is high during the odd field Loss of video signal can be detected by monitoring the C S output The 50% level of the previous video signal will remain held on the S H capacitors after the input video signal has gone and the input on pin 2 has defaulted to the clamp voltage Consequently the C S output will remain low longer than the normal vertical pulse period An external timing circuit could be used to detect this condition Block Diagram 4581 - 4 Figure 5 Note RSET must be a 1% resistor 9 BLANK 10 BLANK 11 EL4581C EL4581C Sync Separator 50% Slice S-H Filter General Disclaimer Specifications contained in this data sheet are in effect as of the publication date shown Elantec Inc reserves the right to make changes in the circuitry or specifications contained herein at any time without notice Elantec Inc assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement WARNING Life Support Policy January 1996 Rev B Elantec Inc 1996 Tarob Court Milpitas CA 95035 Telephone (408) 945-1323 (800) 333-6314 Fax (408) 945-9305 European Office 44-71-482-4596 12 Elantec Inc products are not authorized for and should not be used within Life Support Systems without the specific written consent of Elantec Inc Life Support systems are equipment intended to support or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death Users contemplating application of Elantec Inc products in Life Support Systems are requested to contact Elantec Inc factory headquarters to establish suitable terms conditions for these applications Elantec Inc 's warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages Printed in U S A |
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